Encoder interpolator circuit

ABSTRACT

2M-bit position data is divided into lower-order M-bit data and higher-order M-bit data. The lower-order M-bit data is stored in a lower-order storage area (14a) of a read only memory (ROM) (14), the higher-order M-bit data is stored in a higher-order storage area (14b) of the ROM. The lower-order and higher-order items of M-bit data are read out of the lower-order storage area (14a) and higher-order storage area (14b) by making the most significant bit of address data &#34;0&#34; and &#34;1&#34; successively by way of an address changing unit (15). These items of data are combined by a combining unit (17) to obtain 2M-bit position data.

BACKGROUND OF THE INVENTION

This invention relates to a coder interpolator circuit which outputsmovable element position data by using an A-phase signal and a B-phasesignal.

An absolute position encoder is available which is capable of detecting,as absolute position, the rotational position of a rotary shaft of amotor or the like for driving a machine tool, etc.

FIG. 3 is a block diagram of the interpolator circuit of a prior artabsolute position encoder. An A-phase/B-phase signal generating unit 1is formed by a rotary coding disk, a stationary coding disk, alight-emitting element, a light-receiving element and a signal outputcircuit, none of which are shown. The signal generating unit outputssinusoidal and cosinusoidal A-phase and B-phase signals havingpredetermined cycles per revolution. AD converters 2 and 3 subject theA- and B-phase signals, respectively, to an analog -to- digitalconversion (AD conversion) to obtain address information in the form ofa set of the AD converter output data. Angle data (position data) D_(A)conforming to the A- and B-phase signal levels is read out of thestorage area of a ROM 4 designated by the address information.

Though the foregoing is described with regard to one channel, anarrangement can be adopted in which a plurality of channels havingdifferent numbers of cycles of the A- and B-phase signals are provided.A predetermined number of items of angle information are interpolated inone wavelength of each channel, and the absolute position of a movableelement is detected by using the interpolated data on each channel. Anabsolute position encoder adapted to detect the angle information byusing a plurality of channels having different numbers of cycles hasalready been filed for patent as International Serial No.PCT/JP89/00506.

If the resolution of the AD converters is, say, eight bits, then, whenan A-phase signal K·sinθ and a B-phase signal K·sinθ are subjected to anAD conversion, a resolution in which the result of calculation withregard to the angle θ is 10 bits can be expected.

However, the ROM used in the conventional encoder is one in which theoutput is composed of eight bits; hence, angle data composed of morethan eight bits cannot be delivered as an output. If a ROM having anoutput of 16 bits is used, the expected angle data can be outputted andhighly precise position detection is possible. However, theconfiguration in such case is larger in size and has a greater number ofsignal lines and therefore cannot be employed in an absolute positionencoder which requires a reduced size.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide an encoderinterpolator circuit in which, even if a ROM having an M-bit output isused, data consisting of a maximum of M·2^(m) bits data can be outputtedin equivalent terms.

2M-bit position data is divided into lower-order M-bit data andhigher-order M-bit data. The lower-order M-bit data is stored in alower-order storage area of a ROM, and the higher-order M-bit data isstored in a higher-order storage area of the ROM. The lower-order andhigher-order items of M-bit data are read out of the lower-order storagearea and higher-order storage area by making the most significant bit ofaddress data "0" and "1" successively. These items of data are combinedto obtain 2M-bit position data.

Brief Description of the Drawings

FIG. 1 is a block diagram of an interpolator circuit according to thepresent invention;

FIG. 2 is an operating time chart according to the present invention;and

FIG. 3 is a block diagram of a conventional interpolator circuit.

Description Of The Preferred Embodiment

FIG. 1 is a block diagram of an interpolator circuit in an encoderaccording to the present invention.

Numeral 11 denotes an A-phase/B-phase signal generating unit, which isformed by a rotary coding disk, a stationary coding disk, alight-emitting element, a light-receiving element and a signal outputcircuit (none of which are shown), for outputting a sinusoidal andcosinusoidal A-phase signal VAS and B-phase signal VBS. Numerals 12 and13 denote AD converters having an n-bit (eight bits in FIG. 1)resolution for subjecting the A-phase and B-phase signals VAS and VBS,respectively, to an analog-digital conversion. Numeral 14 designates aROM having (2n+m)-number of address terminals and M-number of outputterminals for storing angle data conforming the A-phase and B-phasesignals. In actuality, the ROM 14 has 2n (n=16) address terminals A₀-A₁₅, an m(m=1) address terminal A₁₆ to which address data ADm isinputted, and output terminals O₀ -O₇ for M (M=8) bits. Lower-ordereight-bit data of the 2·M (M=16)-bit data is stored in the lower-orderstorage area 14a for which the address data ADm is "0", and higher-ordereight-bit data is stored in the higher-order storage area 14b for whichthe address data ADm is " 1". Accordingly, by making the address dataADm, which is applied to the address terminal A16, "0", "1"successively, two items of eight-bit data each are read out of the ROM14 and data consisting of a total of 2·M (M=16) bits can be obtained bycombining these two items of eight-bit data.

Numeral 15 denotes an address changing unit for modifying the addressdata ADm which enters the m(m=1) bit address terminal A₁₆ of the ROM 14.Numeral 16 designates a timing pulse generating unit for generating aclock signal indicating the timing of AD conversion performed by the ADconverters 12 and 13, and the timing of address data modificationperformed by the address changing unit 16. Numeral 17 represents acombining unit for outputting 16-bit angle data upon combining thehigher-order eight bit data and lower-order eight-bit data outputted bythe ROM 14.

FIG. 2 is a timing chart for describing the operation of the presentinvention. AD2n denotes address data of 2n (=16) bits applied to theaddress terminals A₀ -A₁₅ of ROM 14, ADm address data of m (=1) bitapplied to the terminal A₁₆ of ROM 14, and DT data of M (=8) bitsoutputted by the ROM 14.

The overall operation of the present invention will now be described inaccordance with FIGS. 1 and 2.

The first and second AD converters 12 and 13, respectively, subject theA-phase signal VAS and B-phase signal VBS outputted by theA-phase/B-phase signal generating unit 11 to an AD conversion insynchronism with a clock CLK outputted by the timing pulse generatingunit 16. Digital data consisting of a total of 2n (=16) bits outputtedby the AD converters enters the 2n-number of address terminals A₀ -A₁₅of the ROM 14 as address data AD2n. The address changing unit 15 alsoinputs "1" address data ADm to the address terminal A₁₆ of the ROM 14 insynchronism with the clock pulse.

As a result, eight-bit higher-order data DT is read from the outputterminals O₀ -O₇ of ROM 14 and inputted to the combining unit 17, wherethe data is stored in a register 17a.

Thereafter, the address changing unit makes the address data ADm "0" ata predetermined timing and applies this data to the address terminal A₁₆of the ROM 14. As a result, eight-bit lower-order data DT is read fromthe output terminals O₀ -O₇ of ROM 14 and inputted to the combining unit17.

The combining unit 17 combines the higher-order eight-bit data inputtedat the first timing instant and the lower-order eight-bit data inputtedat the next timing instant and outputs, to the next stage, position dataconsisting of a total of 16 bits.

Though the present invention has been described in detail based on anembodiment thereof, the invention is not limited to this embodiment butcan be modified in various ways within the scope of the claims. Forexample, though the invention has been described for a case where m=1, mcan be 2 or more, in which case position data having a maximum of 2^(m)·M bits would be produced.

In accordance with the present invention as described above, digitaldata consisting of a total of 2n bits obtained by subjecting A- andB-phase signals to an analog-digital conversion is inputted as addressdata to 2n-number of address terminals of a ROM, and items of M-bit datasuccessively outputted by the ROM by changing m-bit address datainputted to the remaining address terminals of the ROM are combined toproduce position data. As a result, even if a ROM having an M-bit outputis used, data consisting of a maximum of M·2^(m) bits data can beoutputted in equivalent terms.

I claim:
 1. An interpolator circuit of an encoder for outputtingposition data of a movable element by using an A-phase signal and aB-phase signal, comprising:a ROM having address terminals of (2n+m) bitsand output terminals of M bits, m, n and M being integers greater thanor equal to one, position data conforming to levels of the A-phasesignal and the B-phase signal being stored in the ROM upon being dividedinto M bits; A/D converters, operatively connected to said ROM, having aresolution of n bits for subjecting the A-phase signal and B-phasesignal to an analog-digital conversion and inputting, to 2n-number oflower-order address terminals of the ROM, digital output data consistingof a total of 2n bits obtained by said conversion; an address changingunit, operatively connected to said ROM, for changing address data ofm-number of higher-order bits input to said address terminals of saidROM; and a combining unit, operatively connected to said ROM, forcombining M bits of data successively outputted from said outputterminals of said ROM and outputting 2^(m) ·M bits of position data; theaddress data of the higher-order m bits being successively changed bysaid address changing unit, and M-bit data read from said outputterminals of said ROM by this change being combined to output 2^(m) ·Mbits of position data.
 2. An interpolator circuit of an encoderaccording to claim 1, further comprising a timing signal generatingunit, operatively connected to said A/D converters, for outputting aclock signal indicating analog-digital conversion timing and a clocksignal indicating address data change timing.
 3. An interpolator circuitof an encoder according to claim 1, wherein m=1.